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RS Flip-
Flops
Today's Topic
Sequential Logic Circuits
• RS Flip-Flop
RS (or) SR Flip-Flop
• The S-R flip-flop is basic flip-flop among all the flip-flops.
• All the other flip flops are developed after SR-flip-flop.
• SR flip-flop operates with only positive clock transitions (or) negative
clock transitions.
• Whereas, SR latch operates with enable signal.
• The circuit diagram of SR flip-flop is shown in the following figure.
• This circuit has two inputs S & R and two outputs Q(t)& Q(t)’. The
operation of SR flip flop is similar to SR Latch.
• Consider, this flip-flop affects the outputs only when positive
transition of the clock signal is applied instead of active enable.
SR Latch
Clk S R Q Q’
+ve 0 0 NC NC
+ve 0 1 0 1
+ve 1 0 1 0
+ve 1 1 - -
-ve X X
SR Flip-Flop Truth Table
SR Flip-Flop Truth Table
CLK S R Q Q’ State
+ve 0 0 Q Q’ No Change
+ve 0 1 0 1 RESET
+ve 1 0 1 0 SET
+ve 1 1 1 or 0 0 or 1 Invalid
-ve X X Q Q’ No Change
S R Q(t) Q(t+1) State
0 0 0 0 No Change
0 0 1 1 No Change
0 1 0 0 RESET
0 1 1 0 RESET
1 0 1 1 SET
1 0 0 1 SET
1 1 1 - Invalid
1 1 0 - Invalid
Characteristic Table of S-R Flip-Flop
In Next Class
• D Flip Flop
• A

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Rs flipflop or SR flipFlop

  • 2. Today's Topic Sequential Logic Circuits • RS Flip-Flop
  • 3. RS (or) SR Flip-Flop • The S-R flip-flop is basic flip-flop among all the flip-flops. • All the other flip flops are developed after SR-flip-flop. • SR flip-flop operates with only positive clock transitions (or) negative clock transitions. • Whereas, SR latch operates with enable signal.
  • 4. • The circuit diagram of SR flip-flop is shown in the following figure. • This circuit has two inputs S & R and two outputs Q(t)& Q(t)’. The operation of SR flip flop is similar to SR Latch. • Consider, this flip-flop affects the outputs only when positive transition of the clock signal is applied instead of active enable. SR Latch
  • 5. Clk S R Q Q’ +ve 0 0 NC NC +ve 0 1 0 1 +ve 1 0 1 0 +ve 1 1 - - -ve X X SR Flip-Flop Truth Table
  • 6. SR Flip-Flop Truth Table CLK S R Q Q’ State +ve 0 0 Q Q’ No Change +ve 0 1 0 1 RESET +ve 1 0 1 0 SET +ve 1 1 1 or 0 0 or 1 Invalid -ve X X Q Q’ No Change
  • 7. S R Q(t) Q(t+1) State 0 0 0 0 No Change 0 0 1 1 No Change 0 1 0 0 RESET 0 1 1 0 RESET 1 0 1 1 SET 1 0 0 1 SET 1 1 1 - Invalid 1 1 0 - Invalid Characteristic Table of S-R Flip-Flop
  • 8. In Next Class • D Flip Flop